/**************************************************************************
 *                                                                        *
 *         Copyright (c) 2014 by Generalplus Inc.                         *
 *                                                                        *
 *  This software is copyrighted by and is the property of Generalplus    *
 *  Inc. All rights are reserved by Generalplus Inc.                      *
 *  This software may only be used in accordance with the                 *
 *  corresponding license agreement. Any unauthorized use, duplication,   *
 *  distribution, or disclosure of this software is expressly forbidden.  *
 *                                                                        *
 *  This Copyright notice MUST not be removed or modified without prior   *
 *  written consent of Generalplus Technology Co., Ltd.                   *
 *                                                                        *
 *  Generalplus Inc. reserves the right to modify this software           *
 *  without notice.                                                       *
 *                                                                        *
 *  Generalplus Inc.                                                      *
 *  No.19, Industry E. Rd. IV, Hsinchu Science Park                       *
 *  Hsinchu City 30078, Taiwan, R.O.C.                                    *
 *                                                                        *
 **************************************************************************/
#include "board_config.h"
#include "driver_l1.h"

#define CLK_OFF 0
#define CLK_ON	1

INT8U board_clock_config(void)
{
	// it's do configured here
	enum
	{
		CLK_SYS_BUS = CLK_ON << 0,
		CLK_MEM		= CLK_ON << 1,
		CLK_IRAM	= CLK_ON << 2,
		CLK_MIPI_DSI= CLK_ON << 3,
		CLK_TIMER	= CLK_ON << 4,
		CLK_CPU		= CLK_ON << 5,
		CLK_DA_AD	= CLK_ON << 6,
		CLK_UART_1	= UART1_ENABLE << 7,
		CLK_I2C_0	= I2C0_ENABLE << 8,
		CLK_PSCA_1	= CLK_ON << 9,
		CLK_I2S_RX	= CLK_ON << 10,
		CLK_PSCA_0	= CLK_ON << 11,
		CLK_JPEG_1	= CLK_ON << 12,
		CLK_TFT		= TFT2_ENABLE << 13,
		CLK_ISP		= CLK_ON << 14,
		CLK_SDC_0	= SDC0_ENABLE << 15
	};

	enum
	{
		CLK_RRAM		= CLK_ON << 0,
		CLK_USB_HOST	= CLK_ON << 1,
		CLK_USB_DEVICE	= CLK_ON << 2,
		CLK_CSI_0		= CLK_ON << 3,
		CLK_DMA			= CLK_ON << 4,
		CLK_4202422_0	= CLK_ON << 5,
		CLK_DFB			= CLK_ON << 6,
		CLK_4202422_1	= CLK_ON << 7,
		CLK_SPIFC		= SPIFC_ENABLE << 8,
		CLK_MIPI_A		= CLK_ON << 9,
		CLK_JPEG_0		= CLK_ON << 10,
		CLK_PPU			= CLK_ON << 11,
		CLK_SCALER		= CLK_OFF << 12,
		CLK_LBR			= CLK_ON << 13,
		CLK_MIPI_B		= CLK_ON << 14,
		CLK_SYS_TIMEBASE= CLK_ON << 15
	};

	enum
	{
		CLK_UART_0		= UART0_ENABLE << 0,
		CLK_GPIO		= CLK_ON << 1,
		CLK_IRTC		= CLK_ON << 2,
		CLK_SYS_REG		= CLK_ON << 3,
		CLK_INT			= CLK_ON << 4,
		CLK_SDC_1		= SDC1_ENABLE << 5,
		CLK_SPI_0		= SPI_ENABLE << 6,
		CLK_SPI_1		= SPI_ENABLE << 7,
		CLK_DISP		= CLK_ON << 8,
		CLK_CSI_1		= CLK_OFF << 9,
		CLK_I2C_1		= I2C1_ENABLE << 10,
		CLK_ISP_CLK		= CLK_ON << 11,
		CLK_ROTATOR		= CLK_ON << 12,
		CLK_RES_0		= CLK_OFF << 13,
		CLK_RES_1		= CLK_OFF << 14,
		CLK_RES_2		= CLK_OFF << 15
	};

	enum
	{
		RTC_CLK_SRC_XCKGEN_32K,
		RTC_CLK_SRC_EXTRTC_32K,
		RTC_CLK_SRC = RTC_CLK_SRC_EXTRTC_32K
	};

	// assign & commit
	INT32U sysClockEn0 = 0x0U |
		CLK_SYS_BUS |
		CLK_MEM |
		CLK_IRAM |
		CLK_MIPI_DSI |
		CLK_TIMER |
		CLK_CPU |
		CLK_DA_AD |
		CLK_UART_1 |
		CLK_I2C_0 |
		CLK_PSCA_1 |
		CLK_I2S_RX |
		CLK_PSCA_0 |
		CLK_JPEG_1 |
		CLK_TFT |
		CLK_ISP |
		CLK_SDC_0;
	INT32U sysClockEn1 = 0x0U |
		CLK_RRAM |
		CLK_USB_HOST |
		CLK_USB_DEVICE |
		CLK_CSI_0 |
		CLK_DMA |
		CLK_4202422_0 |
		CLK_DFB |
		CLK_4202422_1 |
		CLK_SPIFC |
		CLK_MIPI_A |
		CLK_JPEG_0 |
		CLK_PPU |
		CLK_SCALER |
		CLK_LBR |
		CLK_MIPI_B |
		CLK_SYS_TIMEBASE;
	INT32U sysClockEn2 = 0x0U |
		CLK_UART_0 |
		CLK_GPIO |
		CLK_IRTC |
		CLK_SYS_REG |
		CLK_INT |
		CLK_SDC_1 |
		CLK_SPI_0 |
		CLK_SPI_1 |
		CLK_DISP |
		CLK_CSI_1 |
		CLK_I2C_1 |
		CLK_ISP_CLK |
		CLK_ROTATOR |
		CLK_RES_0 |
		CLK_RES_1 |
		CLK_RES_2;

	R_SYSTEM_CLK_EN0 = sysClockEn0;
	R_SYSTEM_CLK_EN1 = sysClockEn1;
	R_SYSTEM_CLK_EN2 = sysClockEn2;

	switch(RTC_CLK_SRC)
	{
		case RTC_CLK_SRC_XCKGEN_32K:
			R_SYSTEM_CTRL &= ~(0x1 << 12);
			R_SYSTEM_PLLEN &= ~(0x1 << 8);
		break;
		case RTC_CLK_SRC_EXTRTC_32K:
			R_SYSTEM_CTRL &= ~(0x1 << 12);
			R_SYSTEM_PLLEN |= (0x1 << 8);
		break;
	}

	return MUX_OK;
}

INT8U board_gpio_config()
{
	INT32U	i;

	struct GPIO_DEF
	{
		INT32U port;
		enum
		{
			GPIO_IN_FLOAT,
			GPIO_IN_PULL_LOW,
			GPIO_IN_PULL_HIGH,
			GPIO_OUT_NORMAL,
			GPIO_OUT_INVERT
		} attr;
		BOOLEAN			out_init;
		IO_DRV_LEVEL	out_driving;
	}

	gpio_def[] =
	{

	
		#ifdef TFT_CS_PIN
		{IO_C13,GPIO_OUT_NORMAL,DATA_HIGH, IO_DRIVING_8mA },
		#endif
		
		#if(defined(C_ZHONGQIN_SPECIAL) && (C_ZHONGQIN_SPECIAL == CUSTOM_ON))
			#ifdef MACHINE_STATUS_BLUE_LED
			{MACHINE_STATUS_BLUE_LED,GPIO_OUT_NORMAL,DATA_HIGH, IO_DRIVING_8mA },
			#endif
		#endif
		
		#ifdef CHARGER_IO_LED
		 #if (CHARGER_IO_ACTIVE == DATA_LOW)
		  	{CHARGER_IO_LED,GPIO_OUT_NORMAL,DATA_HIGH, IO_DRIVING_8mA },
		 #else
          		{CHARGER_IO_LED,GPIO_OUT_NORMAL,DATA_LOW, IO_DRIVING_8mA },
		 #endif
		#endif

		#ifdef SPEAKER_EN_PIN
		#if SPEAKER_EN_PIN_ACTIVE
		{ SPEAKER_EN_PIN, GPIO_OUT_NORMAL, DATA_LOW, IO_DRIVING_8mA },
		#else
		{ SPEAKER_EN_PIN, GPIO_OUT_NORMAL, DATA_HIGH, IO_DRIVING_8mA },
		#endif
		#endif

		#ifdef LCD_IO_CSN
		{ LCD_IO_CSN, GPIO_OUT_NORMAL, DATA_HIGH},
		#endif

		#ifdef PANEL_IO_CSN
		{ PANEL_IO_CSN, GPIO_OUT_NORMAL},
		#endif

		#ifdef PANEL_IO_SCL
		{ PANEL_IO_SCL, GPIO_OUT_NORMAL },
		#endif

		#ifdef PANEL_IO_SDA
		{ PANEL_IO_SDA, GPIO_OUT_NORMAL },
		#endif

		#ifdef PANEL_IO_RESET
		{ PANEL_IO_RESET, GPIO_OUT_NORMAL, DATA_HIGH, IO_DRIVING_8mA },
		#endif

		#ifdef BACK_SENSOR_DET
		{ BACK_SENSOR_DET, GPIO_IN_PULL_LOW },
		#endif

		#ifdef USB_PATH_CONTROL
		{ USB_PATH_CONTROL, GPIO_OUT_NORMAL, DATA_LOW, IO_DRIVING_8mA },
		#endif

		#ifdef BACK_SENSOR_PWR
		{ BACK_SENSOR_PWR, GPIO_OUT_NORMAL, DATA_LOW, IO_DRIVING_8mA },
		#endif

		#ifdef PANEL_IO_BL_ON
		{ PANEL_IO_BL_ON, GPIO_OUT_NORMAL, DATA_LOW, IO_DRIVING_8mA },
		#endif

		#ifdef SDC_DETECT_PIN
		{ SDC_DETECT_PIN, GPIO_IN_PULL_HIGH },
		#endif

		{ BACK_SENSOR_LED, GPIO_OUT_NORMAL, DATA_HIGH, IO_DRIVING_8mA },

		

		#ifdef FRONT_SENSOR_RESET
		{ FRONT_SENSOR_RESET, GPIO_OUT_NORMAL, DATA_HIGH, IO_DRIVING_8mA },
		#endif

		#ifdef ACCIN_DETECT_PIN
		{ ACCIN_DETECT_PIN, GPIO_IN_FLOAT },
		#endif

	#if defined(C_FLASH_LIGHT) && C_FLASH_LIGHT 
		#if (FLASH_LIGHT_ACTIVE == DATA_LOW)
		  	{FLASH_LIGHT,GPIO_OUT_NORMAL,DATA_HIGH, IO_DRIVING_16mA },
			  {FLASH_LIGHT_2,GPIO_OUT_NORMAL,DATA_HIGH, IO_DRIVING_16mA },
		 #else
		 	{FLASH_LIGHT,GPIO_OUT_NORMAL,DATA_LOW, IO_DRIVING_16mA },
			  {FLASH_LIGHT_2,GPIO_OUT_NORMAL,DATA_LOW, IO_DRIVING_16mA },
		#endif
	#endif

	};

	for(i = 0; i < sizeof(gpio_def) / sizeof(struct GPIO_DEF); i++)
	{
		switch(gpio_def[i].attr)
		{
		case GPIO_IN_FLOAT:
			{
				gpio_init_io(gpio_def[i].port, GPIO_INPUT);
				gpio_set_port_attribute(gpio_def[i].port, ATTRIBUTE_HIGH);
			}

			break;

		case GPIO_IN_PULL_LOW:
			{
				gpio_init_io(gpio_def[i].port, GPIO_INPUT);
				gpio_set_port_attribute(gpio_def[i].port, ATTRIBUTE_LOW);
				gpio_write_io(gpio_def[i].port, DATA_LOW);
			}

			break;

		case GPIO_IN_PULL_HIGH:
			{
				gpio_init_io(gpio_def[i].port, GPIO_INPUT);
				gpio_set_port_attribute(gpio_def[i].port, ATTRIBUTE_LOW);
				gpio_write_io(gpio_def[i].port, DATA_HIGH);
			}

			break;

		case GPIO_OUT_NORMAL:
			{
				gpio_init_io(gpio_def[i].port, GPIO_OUTPUT);
				gpio_set_port_attribute(gpio_def[i].port, ATTRIBUTE_HIGH);
				gpio_drving_init_io(gpio_def[i].port, gpio_def[i].out_driving);
				gpio_write_io(gpio_def[i].port, gpio_def[i].out_init);
			}

			break;

		case GPIO_OUT_INVERT:
			{
				gpio_init_io(gpio_def[i].port, GPIO_OUTPUT);
				gpio_set_port_attribute(gpio_def[i].port, ATTRIBUTE_LOW);
				gpio_drving_init_io(gpio_def[i].port, gpio_def[i].out_driving);
				gpio_write_io(gpio_def[i].port, gpio_def[i].out_init);
			}

			break;
		}
	}

	return MUX_OK;
}

#if UART0_ENABLE
INT8S uart0_pinmux_set(INT8U idxTx, INT8U idxRx)
{
	INT32U	funpos1 = R_FUNPOS1;
	INT32U	funpos0 = R_FUNPOS0;

	funpos1 &= ~(3 << 16);
	if(idxTx == UART0_TX_MUX0)
	{
		//UART0_TX_IOB5
		funpos1 &= ~(3 << 16);
		gpio_drving_init_io(IO_B5, (IO_DRV_LEVEL) UART0_DRIVING);
	}
	else
	if(idxTx == UART0_TX_MUX1)
	{
		//UART0_TX_IOC12
		funpos1 |= (1 << 16);
		gpio_drving_init_io(IO_C12, (IO_DRV_LEVEL) UART0_DRIVING);
	}
	else
	if(idxTx == UART0_TX_MUX2)
	{
		//UART0_TX_IOC7
		funpos1 |= (2 << 16);
		gpio_drving_init_io(IO_C7, (IO_DRV_LEVEL) UART0_DRIVING);
	}
	else
	if(idxTx == UART0_TX_MUX3)
	{
		//UART0_TX_IOA3
		funpos1 |= (3 << 16);
		gpio_drving_init_io(IO_A3, (IO_DRV_LEVEL) UART0_DRIVING);
	}
	funpos0 &= ~(3 << 0);
	if(idxRx == UART0_RX_MUX0)
	{
		//UART0_RX_IOB4
		funpos0 &= ~(3 << 0);
		gpio_drving_init_io(IO_B4, (IO_DRV_LEVEL) UART0_DRIVING);
	}
	else
	if(idxRx == UART0_RX_MUX1)
	{
		//UART0_RX_IOC13
		funpos0 |= (1 << 0);
		gpio_drving_init_io(IO_C13, (IO_DRV_LEVEL) UART0_DRIVING);
	}
	else
	if(idxRx == UART0_RX_MUX2)
	{
		//UART0_RX_IOC6
		funpos0 |= (2 << 0);
		gpio_drving_init_io(IO_C6, (IO_DRV_LEVEL) UART0_DRIVING);
	}
	else
	if(idxRx == UART0_RX_MUX3)
	{
		//UART0_RX_IOA2
		funpos0 |= (3 << 0);
		gpio_drving_init_io(IO_A2, (IO_DRV_LEVEL) UART0_DRIVING);
	}

	R_FUNPOS1 = funpos1;
	R_FUNPOS0 = funpos0;

	return MUX_OK;
}
#endif

#if UART1_ENABLE
INT8S uart1_pinmux_set(INT8U idxTx, INT8U idxRx)
{
	INT32U	funpos1 = R_FUNPOS1;
	INT32U	funpos0 = R_FUNPOS0;

	funpos1 &= ~(3<<18);
	if(idxTx == UART1_TX_MUX0)
	{
		//UART1_TX_IOA7
		funpos1 &= ~(3 << 18);
		gpio_drving_init_io(IO_A7, (IO_DRV_LEVEL) UART1_DRIVING);
	}
	else
	if(idxTx == UART1_TX_MUX1)
	{
		//UART1_TX_IOA5
		funpos1 |= (1 << 18);
		gpio_drving_init_io(IO_A5, (IO_DRV_LEVEL) UART1_DRIVING);
	}
	else
	if(idxTx == UART1_TX_MUX2)
	{
		//UART1_TX_IOD9
		funpos1 |= (2 << 18);
		gpio_drving_init_io(IO_D9, (IO_DRV_LEVEL) UART1_DRIVING);
	}
	else
	if(idxTx == UART1_TX_MUX3)
	{
		//UART1_TX_IOC5
		funpos1 |= (3 << 18);
		gpio_drving_init_io(IO_C5, (IO_DRV_LEVEL) UART1_DRIVING);
	}
	funpos0 &= ~(3<<2);
	if(idxRx == UART1_RX_MUX0)
	{
		//UART1_RX_IOA6
		funpos0 &= ~(3 << 2);
		gpio_drving_init_io(IO_A6, (IO_DRV_LEVEL) UART1_DRIVING);
	}
	else
	if(idxRx == UART1_RX_MUX1)
	{
		//UART1_RX_IOA4
		funpos0 |= (1 << 2);
		gpio_drving_init_io(IO_A4, (IO_DRV_LEVEL) UART1_DRIVING);
	}
	else
	if(idxRx == UART1_RX_MUX_NONE)
	{
		//UART1_RX_NONE
		funpos0 |= (2 << 2);
	}
	else
	if(idxRx == UART1_RX_MUX3)
	{
		//UART1_RX_IOC4
		funpos0 |= (3 << 2);
		gpio_drving_init_io(IO_C4, (IO_DRV_LEVEL) UART1_DRIVING);
	}

	R_FUNPOS1 = funpos1;
	R_FUNPOS0 = funpos0;

	return MUX_OK;
}
#endif

#if EXT_INT_ENABLE
INT8S ext_int_pinmux_set(INT8U idx)
{
	INT32U funpos0 = R_FUNPOS0;

	funpos0 &= ~(3 << 9);
	if(idx == EXT_INT_MUX0)
	{
		//EXT_INT_A_B_C__IOC3_IOC4_IOC5
		funpos0 &= ~(3 << 9);
		gpio_drving_init_io(IO_C3, (IO_DRV_LEVEL) EXT_INT_DRIVING);
		gpio_drving_init_io(IO_C4, (IO_DRV_LEVEL) EXT_INT_DRIVING);
		gpio_drving_init_io(IO_C5, (IO_DRV_LEVEL) EXT_INT_DRIVING);
	}
	else
	if(idx == EXT_INT_MUX1)
	{
		//EXT_INT_A_B_C__IOC12_IOC13_IOC14
		funpos0 |= (1 << 9);
		gpio_drving_init_io(IO_C12, (IO_DRV_LEVEL) EXT_INT_DRIVING);
		gpio_drving_init_io(IO_C13, (IO_DRV_LEVEL) EXT_INT_DRIVING);
		gpio_drving_init_io(IO_C14, (IO_DRV_LEVEL) EXT_INT_DRIVING);
	}
	else
	if(idx == EXT_INT_MUX2)
	{
		//EXT_INT_A_B_C__IOA4_IOA5_IOA6
		funpos0 |= (2 << 9);
		gpio_drving_init_io(IO_A4, (IO_DRV_LEVEL) EXT_INT_DRIVING);
		gpio_drving_init_io(IO_A5, (IO_DRV_LEVEL) EXT_INT_DRIVING);
		gpio_drving_init_io(IO_A6, (IO_DRV_LEVEL) EXT_INT_DRIVING);
	}
	else
	if(idx == EXT_INT_MUX3)
	{
		//EXT_INT_A_B_C__IOB1_IOB2_IOB3
		funpos0 |= (3 << 9);
		gpio_drving_init_io(IO_B1, (IO_DRV_LEVEL) EXT_INT_DRIVING);
		gpio_drving_init_io(IO_B2, (IO_DRV_LEVEL) EXT_INT_DRIVING);
		gpio_drving_init_io(IO_B3, (IO_DRV_LEVEL) EXT_INT_DRIVING);
	}

	R_FUNPOS0 = funpos0;

	return MUX_OK;
}
#endif //

#if (I2C0_ENABLE || I2C1_ENABLE)
static GPIO_ENUM i2c_gpio_scl[I2C_DEV_NUM];
static GPIO_ENUM i2c_gpio_sda[I2C_DEV_NUM];

GPIO_ENUM pinmux_i2c_scl_get(I2C_DEV dev)
{
	if(dev < I2C_DEV_NUM)
	{
		return i2c_gpio_scl[dev];
	}
	else
	{
		return 0;
	}
}

GPIO_ENUM pinmux_i2c_sda_get(I2C_DEV dev)
{
	if(dev < I2C_DEV_NUM)
	{
		return i2c_gpio_sda[dev];
	}
	else
	{
		return 0;
	}
}
#endif

#if I2C0_ENABLE
INT8S i2c0_pinmux_set(INT8U idx)
{
	INT32U	funpos0 = R_FUNPOS0;

	funpos0 &= ~(3 << 25);
	if(idx == I2C0_MUX0)
	{
		//I2C0_SCL_SDA__IOB4_IOB5
		funpos0 &= ~(3 << 25);

		i2c_gpio_scl[I2C_DEV_0] = IO_B4;
		i2c_gpio_sda[I2C_DEV_0] = IO_B5;
	}
	else
	if(idx == I2C0_MUX1)
	{
		//I2C0_SCL_SDA__IOC12_IOC13
		funpos0 |= (1 << 25);

		i2c_gpio_scl[I2C_DEV_0] = IO_C12;
		i2c_gpio_sda[I2C_DEV_0] = IO_C13;
	}
	else
	if(idx == I2C0_MUX2)
	{
		//I2C0_SCL_SDA__IOA4_IOA5
		funpos0 |= (2 << 25);

		i2c_gpio_scl[I2C_DEV_0] = IO_A4;
		i2c_gpio_sda[I2C_DEV_0] = IO_A5;
	}
	else
	{
		return MUX_ERR;
	}

	// GPIO_IN_PULL_HIGH
	gpio_init_io(i2c_gpio_scl[I2C_DEV_0], GPIO_INPUT);
	gpio_set_port_attribute(i2c_gpio_scl[I2C_DEV_0], ATTRIBUTE_LOW);
	gpio_write_io(i2c_gpio_scl[I2C_DEV_0], DATA_HIGH);

	gpio_init_io(i2c_gpio_sda[I2C_DEV_0], GPIO_INPUT);
	gpio_set_port_attribute(i2c_gpio_sda[I2C_DEV_0], ATTRIBUTE_LOW);
	gpio_write_io(i2c_gpio_sda[I2C_DEV_0], DATA_HIGH);

	gpio_drving_init_io(i2c_gpio_scl[I2C_DEV_0], (IO_DRV_LEVEL) I2C0_DRIVING);
	gpio_drving_init_io(i2c_gpio_sda[I2C_DEV_0], (IO_DRV_LEVEL) I2C0_DRIVING);

	R_FUNPOS0 = funpos0;

	return MUX_OK;
}
#endif

#if I2C1_ENABLE
INT8S i2c1_pinmux_set(INT8U idx)
{
	INT32U	funpos1 = R_FUNPOS1;

	funpos1 &= ~(3 << 14);
	if(idx == I2C1_MUX0)
	{
		//I2C1_SCL_SDA__IOC0_IOC1
		funpos1 &= ~(3 << 14);

		i2c_gpio_scl[I2C_DEV_1] = IO_C0;
		i2c_gpio_sda[I2C_DEV_1] = IO_C1;
	}
	else
	if(idx == I2C1_MUX1)
	{
		//I2C1_SCL_SDA__IOD9_IOD12
		funpos1 |= (1 << 14);

		i2c_gpio_scl[I2C_DEV_1] = IO_D9;
		i2c_gpio_sda[I2C_DEV_1] = IO_D12;
	}
	else
	if(idx == I2C1_MUX1)
	{
		//I2C1_SCL_SDA__IOA6_IOA7
		funpos1 |= (2 << 14);

		i2c_gpio_scl[I2C_DEV_1] = IO_A6;
		i2c_gpio_sda[I2C_DEV_1] = IO_A7;
	}
	else
	{
		return MUX_ERR;
	}

	// GPIO_IN_PULL_HIGH
	gpio_init_io(i2c_gpio_scl[I2C_DEV_1], GPIO_INPUT);
	gpio_set_port_attribute(i2c_gpio_scl[I2C_DEV_1], ATTRIBUTE_LOW);
	gpio_write_io(i2c_gpio_scl[I2C_DEV_1], DATA_HIGH);

	gpio_init_io(i2c_gpio_sda[I2C_DEV_1], GPIO_INPUT);
	gpio_set_port_attribute(i2c_gpio_sda[I2C_DEV_1], ATTRIBUTE_LOW);
	gpio_write_io(i2c_gpio_sda[I2C_DEV_1], DATA_HIGH);

	gpio_drving_init_io(i2c_gpio_scl[I2C_DEV_1], (IO_DRV_LEVEL) I2C1_DRIVING);
	gpio_drving_init_io(i2c_gpio_sda[I2C_DEV_1], (IO_DRV_LEVEL) I2C1_DRIVING);

	R_FUNPOS1 = funpos1;

	return MUX_OK;
}
#endif

#if SPI_ENABLE
INT8S spi_pinmux_set(INT8U idx, INT8U cs_gpio_en)
{
	INT32U	funpos0 = R_FUNPOS0;
	INT32U	gpiofunpos = R_GPIOCTRL;

	funpos0 &= ~(3 << 14);
	if(idx == SPI_MUX0)
	{
		//SPI_CS_CLK_TX_RX__IOC8_IOC9_IOC10_IOC11
		funpos0 &= ~(1 << 14);
		gpio_drving_init_io(IO_C8, (IO_DRV_LEVEL) SPI_DRIVING);
		gpio_drving_init_io(IO_C9, (IO_DRV_LEVEL) SPI_DRIVING);
		gpio_drving_init_io(IO_C10, (IO_DRV_LEVEL) SPI_DRIVING);
	}
	else
	if(idx == SPI_MUX1)
	{
		//SPI_CS_CLK_TX_RX__IOD0_IOD1_IOD2_IOD3
		funpos0 |= (1 << 14);
		gpio_drving_init_io(IO_D0, (IO_DRV_LEVEL) SPI_DRIVING);
		gpio_drving_init_io(IO_D1, (IO_DRV_LEVEL) SPI_DRIVING);
		gpio_drving_init_io(IO_D2, (IO_DRV_LEVEL) SPI_DRIVING);
	}
	else
	if(idx == SPI_MUX2)
	{
		//SPI_CS_CLK_TX_RX__IOD10_IOD11_IOD12_IOD13
		funpos0 |= (2 << 14);
		gpio_drving_init_io(IO_D10, (IO_DRV_LEVEL) SPI_DRIVING);
		gpio_drving_init_io(IO_D11, (IO_DRV_LEVEL) SPI_DRIVING);
		gpio_drving_init_io(IO_D12, (IO_DRV_LEVEL) SPI_DRIVING);
	}
	else
	if(idx == SPI_MUX3)
	{
		//SPI_CS_CLK_TX_RX__IOA6_IOA0_IOA1_IOA4
		funpos0 |= (3 << 14);
		gpio_drving_init_io(IO_A6, (IO_DRV_LEVEL) SPI_DRIVING);
		gpio_drving_init_io(IO_A0, (IO_DRV_LEVEL) SPI_DRIVING);
		gpio_drving_init_io(IO_A1, (IO_DRV_LEVEL) SPI_DRIVING);
	}

	//NOTE: GP15F only SPI0
	if(cs_gpio_en)
	{
		gpiofunpos &= ~(1 << 3);	//SPI CS AS GPIO pin
	}
	else
	{
		gpiofunpos |= (1 << 3);		//SPI CS AS CS pin
	}

	R_FUNPOS0 = funpos0;
	R_GPIOCTRL = gpiofunpos;
	return MUX_OK;
}
#endif

#if SPIFC_ENABLE
INT8S spifc_pinmux_set(INT8U idx)
{
	INT32U	funpos0 = R_FUNPOS0;

	if(idx == SPIFC_MUX0)
	{
		//SPIFC_CS_CLK_RX0_3__IOD0_IOD1_IOD2_IOD3_IOD4_IOD5
		funpos0 &= ~(1 << 30);
		gpio_drving_init_io(IO_D0, (IO_DRV_LEVEL) SPIFC_DRIVING);
		gpio_drving_init_io(IO_D1, (IO_DRV_LEVEL) SPIFC_CLK_DRIVING);
		gpio_drving_init_io(IO_D2, (IO_DRV_LEVEL) SPIFC_DRIVING);
		gpio_drving_init_io(IO_D3, (IO_DRV_LEVEL) SPIFC_DRIVING);
		gpio_drving_init_io(IO_D4, (IO_DRV_LEVEL) SPIFC_DRIVING);
		gpio_drving_init_io(IO_D5, (IO_DRV_LEVEL) SPIFC_DRIVING);
	}
	else
	if(idx == SPIFC_MUX1)
	{
		//SPIFC_CS_CLK_RX0_3__NONE
		funpos0 |= (1 << 30);
	}

	R_FUNPOS0 = funpos0;

	return MUX_OK;
}
#endif

#if SDC0_ENABLE
INT8S sdc0_pinmux_set(INT8U idx)
{
	GPIO_ENUM gpio_cmd, gpio_clk, gpio_data[4];
	INT32U	funpos0 = R_FUNPOS0;

	funpos0 &= ~(3 << 21);
	if(idx == SDC0_MUX0)
	{
		//SDC0_CMD_CLK_DATA0_3__IOA2_IOA3_IOA5_IOA6_IOA7_IOA4
		funpos0 &= ~(3 << 21);

		gpio_cmd = IO_A2;
		gpio_clk = IO_A3;
		gpio_data[0] = IO_A5;
		gpio_data[1] = IO_A6;
		gpio_data[2] = IO_A7;
		gpio_data[3] = IO_A4;
	}
	else
	if(idx == SDC0_MUX1)
	{
		//SDC0_CMD_CLK_DATA0_3__IOC6_IOC7_IOC9_IOC10_IOC11_IOC8
		funpos0 |= (2 << 21);

		gpio_cmd = IO_C6;
		gpio_clk = IO_C7;
		gpio_data[0] = IO_C9;
		gpio_data[1] = IO_C10;
		gpio_data[2] = IO_C11;
		gpio_data[3] = IO_C8;
	}
	else
	if(idx == SDC0_MUX2)
	{
		//SDC0_CMD_CLK_DATA0_3__IOC0_IOC1_IOC3_IOC4_IOC5_IOC2
		funpos0 |= (3 << 21);

		gpio_cmd = IO_C0;
		gpio_clk = IO_C1;
		gpio_data[0] = IO_C3;
		gpio_data[1] = IO_C4;
		gpio_data[2] = IO_C5;
		gpio_data[3] = IO_C2;
 	}

	// GPIO_IN_FLOAT
	gpio_init_io(gpio_clk, GPIO_INPUT);
	gpio_set_port_attribute(gpio_clk, ATTRIBUTE_HIGH);
	gpio_drving_init_io(gpio_clk, (IO_DRV_LEVEL) SDC0_CMD_CLK_DRIVING);

	// GPIO_IN_PULL_HIGH
	gpio_init_io(gpio_cmd, GPIO_INPUT);
	gpio_set_port_attribute(gpio_cmd, ATTRIBUTE_LOW);
	gpio_write_io(gpio_cmd, DATA_HIGH);
	gpio_drving_init_io(gpio_cmd, (IO_DRV_LEVEL) SDC0_CMD_CLK_DRIVING);

	gpio_init_io(gpio_data[0], GPIO_INPUT);
	gpio_set_port_attribute(gpio_data[0], ATTRIBUTE_LOW);
	gpio_write_io(gpio_data[0], DATA_HIGH);
	gpio_drving_init_io(gpio_data[0], (IO_DRV_LEVEL) SDC0_DATA_DRIVING);

	#if SDC_DATA_MODE == SDC_DATA_MODE_4BIT
	gpio_init_io(gpio_data[1], GPIO_INPUT);
	gpio_set_port_attribute(gpio_data[1], ATTRIBUTE_LOW);
	gpio_write_io(gpio_data[1], DATA_HIGH);
	gpio_drving_init_io(gpio_data[1], (IO_DRV_LEVEL) SDC0_DATA_DRIVING);

	gpio_init_io(gpio_data[2], GPIO_INPUT);
	gpio_set_port_attribute(gpio_data[2], ATTRIBUTE_LOW);
	gpio_write_io(gpio_data[2], DATA_HIGH);
	gpio_drving_init_io(gpio_data[2], (IO_DRV_LEVEL) SDC0_DATA_DRIVING);

	gpio_init_io(gpio_data[3], GPIO_INPUT);
	gpio_set_port_attribute(gpio_data[3], ATTRIBUTE_LOW);
	gpio_write_io(gpio_data[3], DATA_HIGH);
	gpio_drving_init_io(gpio_data[3], (IO_DRV_LEVEL) SDC0_DATA_DRIVING);
	#endif

	R_FUNPOS0 = funpos0;
	return MUX_OK;
}
#endif

#if SDC1_ENABLE
INT8S sdc1_pinmux_set(INT8U idx)
{
	GPIO_ENUM gpio_cmd, gpio_clk, gpio_data[4];
	INT32U	funpos0 = R_FUNPOS0;

	funpos0 &= ~(3 << 23);
	if(idx == SDC1_MUX0)
	{
		//SDC1_CMD_CLK_DATA0_3__IOD10_IOD11_IOD13_IOC14_IOC15_IOC13
		funpos0 |= (2 << 23);

		gpio_cmd = IO_D10;
		gpio_clk = IO_D11;
		gpio_data[0] = IO_D13;
		gpio_data[1] = IO_C14;
		gpio_data[2] = IO_C15;
		gpio_data[3] = IO_C13;
	}
	else
	if(idx == SDC1_MUX1)
	{
		//SDC1_CMD_CLK_DATA0_3__IODB2_IOB1_IOB3_NONE_NONE_NONE
		funpos0 |= (1 << 23);

		gpio_cmd = IO_B2;
		gpio_clk = IO_B1;
		gpio_data[0] = IO_B3;
		gpio_data[1] = IO_F15;
		gpio_data[2] = IO_F15;
		gpio_data[3] = IO_F15;
	}

	// GPIO_IN_FLOAT
	gpio_init_io(gpio_clk, GPIO_INPUT);
	gpio_set_port_attribute(gpio_clk, ATTRIBUTE_HIGH);
	gpio_drving_init_io(gpio_cmd, (IO_DRV_LEVEL) SDC1_CMD_CLK_DRIVING);

	// GPIO_IN_PULL_HIGH
	gpio_init_io(gpio_cmd, GPIO_INPUT);
	gpio_set_port_attribute(gpio_cmd, ATTRIBUTE_LOW);
	gpio_write_io(gpio_cmd, DATA_HIGH);
	gpio_drving_init_io(gpio_clk, (IO_DRV_LEVEL) SDC1_CMD_CLK_DRIVING);

	gpio_init_io(gpio_data[0], GPIO_INPUT);
	gpio_set_port_attribute(gpio_data[0], ATTRIBUTE_LOW);
	gpio_write_io(gpio_data[0], DATA_HIGH);
	gpio_drving_init_io(gpio_data[0], (IO_DRV_LEVEL) SDC1_DATA_DRIVING);

	#if SDC_DATA_MODE == SDC_DATA_MODE_4BIT
	gpio_init_io(gpio_data[1], GPIO_INPUT);
	gpio_set_port_attribute(gpio_data[1], ATTRIBUTE_LOW);
	gpio_write_io(gpio_data[1], DATA_HIGH);
	gpio_drving_init_io(gpio_data[1], (IO_DRV_LEVEL) SDC1_DATA_DRIVING);

	gpio_init_io(gpio_data[2], GPIO_INPUT);
	gpio_set_port_attribute(gpio_data[2], ATTRIBUTE_LOW);
	gpio_write_io(gpio_data[2], DATA_HIGH);
	gpio_drving_init_io(gpio_data[2], (IO_DRV_LEVEL) SDC1_DATA_DRIVING);

	gpio_init_io(gpio_data[3], GPIO_INPUT);
	gpio_set_port_attribute(gpio_data[3], ATTRIBUTE_LOW);
	gpio_write_io(gpio_data[3], DATA_HIGH);
	gpio_drving_init_io(gpio_data[3], (IO_DRV_LEVEL) SDC1_DATA_DRIVING);
	#endif


	R_FUNPOS0 = funpos0;

	return MUX_OK;
}
#endif

#if TFT2_ENABLE
static GPIO_ENUM tft_gpio_de;
static GPIO_ENUM tft_gpio_hsync;
static GPIO_ENUM tft_gpio_vsync;
static GPIO_ENUM tft_gpio_clk;

GPIO_ENUM pinmux_tft_de_get(void)
{
	return tft_gpio_de;
}

GPIO_ENUM pinmux_tft_hsync_get(void)
{
	return tft_gpio_hsync;
}

GPIO_ENUM pinmux_tft_vsync_get(void)
{
	return tft_gpio_vsync;
}

GPIO_ENUM pinmux_tft_clk_get(void)
{
	return tft_gpio_clk;
}

INT8S tft_pinmux_set(INT8U ctrl_mux, INT8U ldata_mux, INT8U hdata_mux)
{
	INT32U	funpos0 = R_FUNPOS0;

	funpos0 &= ~(1 << 27);

	if(ldata_mux == TFT_DATA0_7_MUX0)
	{
		//TFT_DATA_0_7__IOA0_IOA7
		funpos0 &= ~(1 << 27);
		gpio_drving_init_io(IO_A0, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_A1, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_A2, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_A3, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_A4, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_A5, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_A6, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_A7, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
	}
	else
	if(ldata_mux == TFT_DATA0_7_MUX1)
	{
		//TFT_DATA_0_7__IOC0_IOC7
		funpos0 |= (1 << 27);
		gpio_drving_init_io(IO_C0, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C1, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C2, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C3, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C4, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C5, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C6, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C7, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
	}

	if(hdata_mux == TFT_DATA8_15_MUX0)
	{
		//TFT_DATA_8_15__IOC0_IOC7
		gpio_drving_init_io(IO_C0, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C1, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C2, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C3, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C4, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C5, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C6, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
		gpio_drving_init_io(IO_C7, (IO_DRV_LEVEL) TFT_DATA_DRIVING);
	}

	if(ctrl_mux == TFT_CTRL_MUX0)
	{
		//TFT_CTRL_DE_HSYNC_VSYNC_CLK__NONE_IOB1_IOB2_IOB3
		funpos0 &= ~(1 << 13);

		tft_gpio_de		= IO_F15;
		tft_gpio_hsync	= IO_B1;
		tft_gpio_vsync	= IO_B2;
		tft_gpio_clk	= IO_B3;
	}
	else
	if(ctrl_mux == TFT_CTRL_MUX1)
	{
		//TFT_CTRL_DE_HSYNC_VSYNC_CLK__IOC8_IOC9_IOC10_IOC11
		funpos0 |= (1 << 13);

		tft_gpio_de		= IO_C8;
		tft_gpio_hsync	= IO_C9;
		tft_gpio_vsync	= IO_C10;
		tft_gpio_clk	= IO_C11;
	}

	gpio_drving_init_io(tft_gpio_clk, (IO_DRV_LEVEL) TFT_CLK_DRIVING);

	R_FUNPOS0 = funpos0;

	return MUX_OK;
}
#endif

#if CSI_CLKO_ENABLE
INT8S csi_clko_set(INT8U clko_mux, INT8U clko_src)
{
	INT32U	funpos1 = R_FUNPOS1;

	funpos1 &= ~(0x0F << 24);
	funpos1 &= ~(0x0F << 20);

	if(clko_mux == CSI_CLKO_MUX0)
	{
		//CSI_MIPI_CLKO__IOC9
		funpos1 |= (1 << 20);
		if(clko_src == CLK_SOURCE_FROM_CSIMCLK)
		{
			funpos1 |= (1 << 24);
		}
		gpio_drving_init_io(IO_C9, (IO_DRV_LEVEL) CSI_CLKO_DRIVING);
	}
	else
	if(clko_mux == CSI_CLKO_MUX1)
	{
		//CSI_MIPI_CLKO__IOD9
		funpos1 |= (1 << 21);
		if(clko_src == CLK_SOURCE_FROM_CSIMCLK)
		{
			funpos1 |= (1 << 25);
		}
		gpio_drving_init_io(IO_D9, (IO_DRV_LEVEL) CSI_CLKO_DRIVING);
	}
	else
	if(clko_mux == CSI_CLKO_MUX2)
	{
		//CSI_MIPI_CLKO__IOD12
		funpos1 |= (1 << 22);
		if(clko_src == CLK_SOURCE_FROM_CSIMCLK)
		{
			funpos1 |= (1 << 26);
		}
		gpio_drving_init_io(IO_D12, (IO_DRV_LEVEL) CSI_CLKO_DRIVING);
	}
	else
	if(clko_mux == CSI_CLKO_MUX3)
	{
		//CSI_MIPI_CLKO__IOB5
		funpos1 |= (1 << 23);
		if(clko_src == CLK_SOURCE_FROM_CSIMCLK)
		{
			funpos1 |= (1 << 27);
		}
		gpio_drving_init_io(IO_B5, (IO_DRV_LEVEL) CSI_CLKO_DRIVING);
	}

	R_FUNPOS1 = funpos1;

	return MUX_OK;
}
#endif

#if CSI_ENABLE
INT8S csi_pinmux_set(INT8U ctrl_mux, INT8U data_mux)
{
	INT32U	funpos1 = R_FUNPOS1;

	funpos1 &= ~(0x1E << 0);

	if(ctrl_mux == CSI_CTRL_MUX0)
	{
		//CSI_CTRL_CLKI_HSYNC_VSYNC__IOC8_IOC10_IOC11
		funpos1 &= ~(1 << 1);
	}
	else
	if(ctrl_mux == CSI_CTRL_MUX1)
	{
		//CSI_CTRL_CLKI_HSYNC_VSYNC__IOD10_IOD12_IOD13
		funpos1 |= (1 << 1);
	}
	else
	if(ctrl_mux == CSI_CTRL_MUX2)
	{
		//CSI_CTRL_CLKI_HSYNC_VSYNC__IOB2_IOC14_IOC15
		funpos1 |= (2 << 1);
	}

	if(data_mux == CSI_DATA2_9_MUX0)
	{
		//CSI_DATA_2_9__IOC0_IOC7
		funpos1 &= ~(3 << 3);
	}
	else
	if(data_mux == CSI_DATA2_9_MUX1)
	{
		//CSI_DATA_2_9__IOC14_IOC15_IOA2_IOA7
		funpos1 |= (1 << 3);
	}
	else
	if(data_mux == CSI_DATA2_9_MUX2)
	{
		//CSI_DATA_2_9__IOC11_IOC9_IOC8_IOC10_IOB1_IOB3_IOB4_IOC13
		funpos1 |= (2 << 3);
	}

	R_FUNPOS1 = funpos1;

	return MUX_OK;
}
#endif

#if CDSP_CLKO_ENABLE
INT8S cdsp_clko_set(INT8U clko_mux, INT8U clko_src)
{
	INT32U	funpos1 = R_FUNPOS1;
	funpos1 &= ~(0x0F << 24);
	funpos1 &= ~(0x0F << 20);

	if(clko_mux == CDSP_CLKO_MUX0)
	{
		//CDSP_CLKO__IOC9
		funpos1 |= (1 << 20);
		if(clko_src == CLK_SOURCE_FROM_CSIMCLK)
		{
			funpos1 |= (1 << 24);
		}
		gpio_drving_init_io(IO_C9, (IO_DRV_LEVEL) CDSP_CLKO_DRIVING);
	}
	else
	if(clko_mux == CDSP_CLKO_MUX1)
	{
		//CDSP_CLKO__IOD9
		funpos1 |= (1 << 21);
		if(clko_src == CLK_SOURCE_FROM_CSIMCLK)
		{
			funpos1 |= (1 << 25);
		}
		gpio_drving_init_io(IO_D9, (IO_DRV_LEVEL) CDSP_CLKO_DRIVING);
	}
	else
	if(clko_mux == CDSP_CLKO_MUX2)
	{
		//CDSP_CLKO__IOD12
		funpos1 |= (1 << 22);
		if(clko_src == CLK_SOURCE_FROM_CSIMCLK)
		{
			funpos1 |= (1 << 26);
		}
		gpio_drving_init_io(IO_D12, (IO_DRV_LEVEL) CDSP_CLKO_DRIVING);
	}
	else
	if(clko_mux == CDSP_CLKO_MUX3)
	{
		//CDSP_CLKO__IOB5
		funpos1 |= (1 << 23);
		if(clko_src == CLK_SOURCE_FROM_CSIMCLK)
		{
			funpos1 |= (1 << 27);
		}
		gpio_drving_init_io(IO_B5, (IO_DRV_LEVEL) CDSP_CLKO_DRIVING);
	}
	R_FUNPOS1 = funpos1;

	return MUX_OK;
}
#endif

#if CDSP_ENABLE
INT8S cdsp_pinmux_set(INT8U ctrl_mux, INT8U hdata_mux, INT8U ldata_mux)
{
	INT32U	funpos1 = R_FUNPOS1;
	INT32U	gpioctrl = R_GPIOCTRL;

	funpos1 &= ~(0x3F << 6);

	if(ctrl_mux == CDSP_CTRL_MUX0)
	{
		//CDSP_CTRL_CLKI_HSYNC_VSYNC__IOC8_IOC10_IOC11
		funpos1 &= ~(0x03 << 6);
	}
	else
	if(ctrl_mux == CDSP_CTRL_MUX1)
	{
		//CDSP_CTRL_CLKI_HSYNC_VSYNC__IOD10_IOD12_IOD13
		funpos1 |= (1 << 6);
	}
	else
	if(ctrl_mux == CDSP_CTRL_MUX2)
	{
		//CDSP_CTRL_CLKI_HSYNC_VSYNC__IOB2_IOC14_IOC15
		funpos1 |= (2 << 6);
	}

	if(hdata_mux == CDSP_DATA2_9_MUX0)
	{
		//CDSP_DATA_2_9__IOC0_IOC7
		funpos1 &= ~(3 << 8);
	}
	else
	if(hdata_mux == CDSP_DATA2_9_MUX1)
	{
		//CDSP_DATA_2_9__IOC14_IOC15_IOA2_IOA7
		funpos1 |= (1 << 8);
	}
	else
	if(hdata_mux == CDSP_DATA2_9_MUX2)
	{
		//CDSP_DATA_2_9__IOC11_IOC9_IOC8_IOC10_IOB1_IOB3_IOB4_IOC13
		funpos1 |= (2 << 8);
	}

	gpioctrl &= ~(1 << 1);

	if(ldata_mux == CDSP_DATA0_1_MUX0)
	{
		//CDSP_DATA_0_1__IOB4_IOB5
		funpos1 |= (1 << 10);
	}
	else
	if(ldata_mux == CDSP_DATA0_1_MUX1)
	{
		//CDSP_DATA_0_1__IOC12_IOC13
		funpos1 |= (2 << 10);
	}
	else
	if(ldata_mux == CDSP_DATA0_1_MUX_NONE)
	{
		//CDSP_DATA_0_1_NONE
		funpos1 &= ~(3 << 10);
	}

	R_FUNPOS1 = funpos1;
	R_GPIOCTRL = gpioctrl;

	return MUX_OK;
}
#endif

#if TIMER_CCP_ENABLE
INT8S timer_ccp_pinmux_set(INT8U idx)
{
	INT32U	funpos0 = R_FUNPOS0;

	funpos0 &= ~(0x0F << 5);

	if(idx == TIMER_CCP_MUX0)
	{
		//TIMER_A_TO_H_CCP__IOC0_IOC1_IOC2_IOC3_IOC4_IOC5_IOC6_IOC7
		funpos0 &= ~(0x0F << 5);
		gpio_drving_init_io(IO_C0, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C1, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C2, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C3, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C4, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C5, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C6, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C7, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
	}
	else
	if(idx == TIMER_CCP_MUX1)
	{
		//TIMER_A_TO_H_CCP__IOD2_IOD3_IOD9_IOD12_IOB2_IOB3_IOB4_IOB5
		funpos0 |= (0x05 << 5);
		gpio_drving_init_io(IO_D2, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_D3, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_D9, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_D12, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_B2, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_B3, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_B4, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_B5, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
	}
	else
	if(idx == TIMER_CCP_MUX2)
	{
		//TIMER_A_TO_H_CCP__IOC8_IOC9_IOC10_IOC11_IOC12_IOC13_IOC14_IOC15
		funpos0 |= (0x0A << 5);
		gpio_drving_init_io(IO_C8, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C9, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C10, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C11, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C12, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C13, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C14, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_C15, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
	}
	else
	if(idx == TIMER_CCP_MUX3)
	{
		//TIMER_A_TO_H_CCP__IOA0_IOA1_IOA2_IOA3_IOA4_IOA5_IOA6_IOA7
		funpos0 |= (0x0F << 5);
		gpio_drving_init_io(IO_A0, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_A1, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_A2, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_A3, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_A4, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_A5, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_A6, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
		gpio_drving_init_io(IO_A7, (IO_DRV_LEVEL) TIMER_CCP_DRIVING);
	}
	R_FUNPOS0 = funpos0;
	return MUX_OK;
}
#endif

void board_init(void)
{
	#if TFT2_ENABLE
	tft_pinmux_set(TFT_CTRL_POS, TFT_DATA_0_7_POS, TFT_DATA_8_15_POS);
	#endif

	#if CSI_ENABLE
	csi_pinmux_set(CSI_CTRL_POS, CSI_DATA_2_9_POS);
	#endif

	#if CDSP_ENABLE
	cdsp_pinmux_set(CDSP_CTRL_POS, CDSP_DATA_2_9_POS, CDSP_DATA_0_1_POS);
	#endif

	#if CSI_CLKO_ENABLE
	csi_clko_set(CSI_CLKO_POS,CSI_CLKO_SOURCE);
	#endif

	#if CDSP_CLKO_ENABLE
	cdsp_clko_set(CDSP_CLKO_POS,CDSP_CLKO_SOURCE);
	#endif

	#if UART0_ENABLE
	uart0_pinmux_set(UART0_TX_POS,UART0_RX_POS);
	#endif

	#if UART1_ENABLE
	uart1_pinmux_set(UART1_TX_POS,UART1_RX_POS);
	#endif

	#if EXT_INT_ENABLE
	ext_int_pinmux_set(EXT_INT_POS);
	#endif

	#if I2C0_ENABLE
	i2c0_pinmux_set(I2C0_POS);
	#endif

	#if I2C1_ENABLE
	i2c1_pinmux_set(I2C1_POS);
	#endif

	#if SPI_ENABLE
	spi_pinmux_set(SPI_POS, SPI_CS_GPIO_MODE);
	#endif

	#if SPIFC_ENABLE
	spifc_pinmux_set(SPIFC_POS);
	#endif

	#if SDC0_ENABLE
	sdc0_pinmux_set(SDC0_POS);
	#endif

	#if SDC1_ENABLE
	sdc1_pinmux_set(SDC1_POS);
	#endif

	#if TIMER_CCP_ENABLE
	timer_ccp_pinmux_set(TIMER_CCP_POS);
	#endif

	board_gpio_config();

	board_clock_config();
}
